Hello,
I am trying to build an interface to a Analog Devices AD5447 digital analog converter on Xilinx Virtex-II 1000 and 3000 FPGAs. First the interface seems to work because the DAC outputs a sinus signal as supposed to do. Now as the design is getting bigger more and more noise is shown on the dac output. So I think this is related to timing issues concerning the dac interface.
The AD5447 needs a clock signal (named CS) with a CS low time of minimal 10 ns and a CS high time of 7 ns minimal. I generate this signal using the recommended clock forwarding scheme consisting of a DCM with CLK0 and CLK180 BUFGs (each with a period of 20 ns, duty cycle correction, source synchronous timing) driving an DDR register in the IOB (first output is '0' to get a clock corresponding to the CLK180 DCM output).
The DAC data setup time is 7 ns minimum before the rising edge of CS and the data hold time is 0 ns minimum. The data is clocked with the DCM CLK0 output to the IOBs. So at a rising edge of CLK0 the data is presented to the DAC and at a rising edge of CLK180(=CS) the data is sampled from the DAC.
Now how do I get the data signals generated by a Xilinx DDS IP Core synchronized to the CS signal to met the timing requirements mentioned above? Particularly how to constrain the data path to the IOBs to meet a maximal delay of 3 ns behind the DCM CLK0 output?
A "OFFSET OUT" constraint of 3ns seems not to work because of too long IOB path delays.
Can this problem be solved with timing constraints or do I have to implement a clocking scheme with to distinct clocks, one for data generation and one to send the data together with a clock to the DAC?
Thanks for your help.
Best regards, S. Hagenkoetter.