Hi, Thanks for replying. I want to design 32 bit to 64 bit multipliers, so I can not use just one 18x18 bit XtremeDSP slice.
In my experiments, I am looking at how the shape of multipliers affect their partial reconfiguration. This is when we do difference based partial reconfiguration of the multiplier. If these multipliers do not mix with other components and routing remains same, then when they are reconfigured to new multiplier of same shape, lots of reconfiguration bits can be saved.
Dsp slices based multiplier will be location-constrained which I do not want, as I want the multiplier to be placed anywhere in the area.
I know that ISE 8.1 is now supporting module-based partial reconfiguration using PlanAhead 8.1. But I am looking at saving the reconfiguration bits inside the PRM part (which may internally consists of multipliers and other components) of the design using difference-based scheme.
Hence, I need to specify to Xilinx floorplanner to not to mix the logic of multiplier with other logic. Is there a way to specify such constraint in UCF file without explicitly specifying location constraints? For getting similar shapes of multiplier, I wanted to specify RPM constraints for the multipliers but I could not do it for Virtex 4. So I was curious if this is a known limitation.
Thanks, Love Singhal