I am using Xilinx Core Generator (ISE 6.1 version) for creating memory modules for the Xilinx Virtex II pro family.
I saw that in case the size of the memory is large such that 2 or more RAMBs are utilized, the resulting module is not RPMed even though the create RPM option in the CORE generator is checked. I have to go manually to the .edn file created by the generator and put the "RLOC" and "RPM_GRID" properties for the RAMB instances myself. Then after ngdbuild and map, the module is recognized as RPM.
What is the reason for this? Is there any other solution other than what I just mentioned above?
Also... I use the Xilinx Development System from the command line and like to use EMACS. What should I include in my .emacs file so as to enable syntax highlighting for UCF, XCF and other relavant files like in the Xilinx ISE editor?
Eagerly awaiting replies... Thanks, Akshay.