I noticed that there's the capability in the floorplanner to create an RPM from a floorplanned design.
I tried floorplanning some of the lower-level modules, and then saving them into the [module].ucf file, but the higher-level modules (those that instantiate the lower ones :-) didn't seem to pick up on the RPM availability.
Is there something I have to do in the high-level module to tell ISE to use the RPM ? I'm using verilog and XST if that matters ?
Move middle.v to a separate directory. Synthesize it with xst to generate a ngc file (turn off I/O buffer insertion if needed). This ngc file does NOT have RPM info. Run floorplanner to floorplan the middle module and write out RPM constraints to middle.ucf. Now run ngcbuild (not ngdbuild) on the ngc file that xst generated. ngcbuild will read in middle.ucf and middle.ngc to create a new ngc file. This ngc file will have RPM info. You need to delete the old middle.ngc and rename the new ngc to middle.ngc.
Move lower.v to another directory and do the same thing as above.
Create two black box module files middle_bb.v and lower_bb.v with the same module name as middle.v and lower.v respectively and only the port definitions. In top.v, instantiate the two black boxes. Include the two black box files with your ISE project. Now run xst on top.v. Before you run translate (ngdbuild) on top.v, use -sd option to specify search path for the cores that were created. Then complete the implementation.
HTH, Jim ( snipped-for-privacy@yahoo.com remove NOOOSPAM)
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