Hi,
I have some trouble when I try to generate a RPM using the floorplanner tool in Xilinx. I'm trying to make a RPM from a quite large design but cannot get it to work. Now I'm trying with a simplified sub-module of my design (see below). The merge_test entity is a simple demux with 3 select signals for each data signal.
When I synthesize and implement in Xilinx ISE I use the standard settings except that I unchecks the insertion of I/O buffers and trimming of unconnected signals.
After PAR I load the design into floorplanner and selects floorplan-
replace all with placement.
I get the first problem after executing "replace all with placement". Two gates in the Design Hierarchy window is still unplaced! I have to place them manually to get them included in the RPM.
Next issue: When I count the number of LUTs showing up in floorplanner I only get
18 LUTs including the two unplaced gates. Two LUTs are missing! So I loads the design into FPGA Editor and I'm able to locate all 20 LUTs. The four problematic LUTs are the 4 3-input OR-gates for or-ing the select signals together. The four problematic are all marked as "Route Through"s in FPGA Editor.
What are a route through? How do I get all LUTs to show up and get placed in floorplanner so I'm able to generate an RPM of the design?
The target is a Xilinx Virtex-5 FPGA.
Any help is appreciated.
Kind Regards Jon Neerup Lassen
------ BEGIN VHDL -------
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity merge_test is port(
a0,a1,a2 : in std_logic; b0,b1,b2 : in std_logic; c0,c1,c2 : in std_logic; d0,d1,d2 : in std_logic;
a_data : in std_logic_vector(7 downto 0); b_data : in std_logic_vector(7 downto 0); c_data : in std_logic_vector(7 downto 0); d_data : in std_logic_vector(7 downto 0);
z_data : out std_logic_vector(7 downto 0)
); end merge_test;
architecture arch of merge_test is
signal a,b,c,d : std_logic;
begin
data_demux : process(a0,a1,a2,b0,b1,b2,c0,c1,c2,d0,d1,d2,a_data,b_data,c_data,d_data) begin if (a0 or a1 or a2) = '1' then z_data