Yes this is possible.
See our downloadable design examples, specifically the clocks file, I haves assumed Xilinx and XST flow etc.
This does more than what you want, as it synchronises some external SDRAM memorys too.
rs_sys comes from an input buffer (IBUF) etc.
Good Luck
----------------------------------------------------------------------------
----------
-- (c) Copyright [2003] ExpressIP Ltd. All rights reserved.
----------------------------------------------------------------------------
----------
-- The copyright in this material is owned by ExpressIP Ltd ("ExpressIP").
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-- The contents of this file are subject to the ExpressIP License Agreement.
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-- You may not use this file except in compliance with the ExpressIP Licence Agreement.
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-- The ExpressIP Licence Agreement is to be used over and above all other agreements.
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-- This source file may be used and distributed subject to the
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----------------------------------------------------------------------------
----------
----------------------------------------------------------------------------
---------- --
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
-- synthesis translate_off LIBRARY unisim; USE unisim.ALL;
-- synthesis translate_on
ENTITY ExpressIP_clks IS PORT( ra_sys : IN STD_LOGIC ; -- System asynchronous reset. cki_sys : IN STD_LOGIC ; -- 27MHz raw clock in from osc. ckr_sys : OUT STD_LOGIC ; -- 54MHZ (x2) System clock output for use inside FPGA, clock tree output.
cki_capt : IN STD_LOGIC ; -- capture clock. ckr_capt : OUT STD_LOGIC ; -- capture clock. ckr_capt_dir : OUT STD_LOGIC ; -- capture clock direct.
cko_54MHz_1 : OUT STD_LOGIC ; -- 54MHZ (x2) System clock output for use outside FPGA, with sdrams. cki_54MHz_1 : IN STD_LOGIC ; -- feedback version of cko_54MHz_1 for DLL in EpressIP_clks.vhd, used to synchronise the clocks.
cko_54MHz_2 : OUT STD_LOGIC ; -- 54MHZ (x2) System clock output for use outside FPGA, with sdrams. cki_54MHz_2 : IN STD_LOGIC ; -- feedback version of cko_54MHz_2 for DLL in EpressIP_clks.vhd, used to synchronise the clocks.
op_dlls_capt_locked : OUT STD_LOGIC ; -- indicates the DLL's are settled op_dlls_locked_extd : OUT STD_LOGIC ; -- indicates the DLL's are settled but delayed so that the pulse can be used in a state machine etc. op_dlls_locked : OUT -- indicates the DLL's are settled. ); END ExpressIP_clks;
ARCHITECTURE asic OF ExpressIP_clks IS
COMPONENT CLKDLL PORT (clkin, clkfb, rst : IN STD_LOGIC; clk0, clk90, clk180, clk270, clk2x, clkdv, locked : OUT STD_LOGIC); END COMPONENT;
COMPONENT IBUFG PORT (I : IN STD_LOGIC; O : OUT STD_LOGIC); END COMPONENT;
COMPONENT BUFG PORT (I : IN STD_LOGIC; O : OUT STD_LOGIC); END COMPONENT;
COMPONENT OBUF PORT (I : IN STD_LOGIC; O : OUT STD_LOGIC); END COMPONENT;
COMPONENT SRL16E PORT (D : IN STD_LOGIC ; CLK : IN STD_LOGIC ; Q : OUT STD_LOGIC ; CE : IN STD_LOGIC ; A3 : IN STD_LOGIC ; A2 : IN STD_LOGIC ; A1 : IN STD_LOGIC ; A0 : IN STD_LOGIC ); END COMPONENT;
SIGNAL s_ra_sys : STD_LOGIC ;
SIGNAL s_logic1 : STD_LOGIC := '1' ; SIGNAL s_clk_in_ibuf : STD_LOGIC ; SIGNAL s_clk_fb_ibuf : STD_LOGIC ; SIGNAL s_clk_108_ibuf : STD_LOGIC ; SIGNAL s_clk_dllx2_ext : STD_LOGIC ; SIGNAL s_dll_locked_ext : STD_LOGIC ; SIGNAL s_cko_54MHz : STD_LOGIC ; SIGNAL s_clk_dllx2_int : STD_LOGIC ; SIGNAL s_dll_locked_int : STD_LOGIC ; SIGNAL s_clk_a_out : STD_LOGIC ; SIGNAL s_clk_dllx4_int : STD_LOGIC ; SIGNAL s_clk_108_out : STD_LOGIC ; SIGNAL s_clk_dllx4_ext : STD_LOGIC ; SIGNAL s_op_dlls_locked : STD_LOGIC ; SIGNAL s_dll_locked_int_dly : STD_LOGIC ; SIGNAL s_dll_locked_int_dly_inv : STD_LOGIC ; SIGNAL s_dll_locked_ext_dly : STD_LOGIC ; SIGNAL s_dll_locked_ext_dly_inv : STD_LOGIC ; SIGNAL s_op_dlls_locked_extd : STD_LOGIC ; SIGNAL s_op_dlls_locked_extdd : STD_LOGIC ; SIGNAL s_dll_locked_108int : STD_LOGIC ; SIGNAL s_read_addr : STD_LOGIC_VECTOR(3 DOWNTO 0) ;
SIGNAL s_clk_capt_ibuf : STD_LOGIC ; SIGNAL s_clk_capt_int : STD_LOGIC ; SIGNAL s_clk_capt_out : STD_LOGIC ; SIGNAL s_dll_locked_capt : STD_LOGIC ;
BEGIN
s_ra_sys cki_sys , O => s_clk_in_ibuf );
ibufg_i1 : IBUFG PORT MAP ( I => cki_54MHz_1 , O => s_clk_fb_ibuf );
ibufg_i2 : IBUFG PORT MAP ( I => cki_54MHz_2 , O => s_clk_108_ibuf );
clkdll_i0 : CLKDLL PORT MAP ( CLKIN => s_clk_in_ibuf , CLKFB => s_clk_a_out , RST => s_ra_sys , CLK2X => s_clk_dllx2_int , clk0 => OPEN , clk90 => OPEN , clk180 => OPEN , clk270 => OPEN , clkdv => OPEN , LOCKED => s_dll_locked_int );
bufg0 : BUFG PORT MAP ( I => s_clk_dllx2_int , O => s_clk_a_out );
ckr_sys s_clk_in_ibuf , D => s_dll_locked_int , Q => s_dll_locked_int_dly , CE => s_logic1 , A3 => s_read_addr(3) , A2 => s_read_addr(2) , A1 => s_read_addr(1) , A0 => s_read_addr(0) );
s_dll_locked_int_dly_inv s_clk_a_out , CLKFB => s_clk_fb_ibuf , RST => s_dll_locked_int_dly_inv , CLK2X => s_clk_dllx4_ext , clk0 => s_clk_dllx2_ext , clk90 => OPEN , clk180 => OPEN , clk270 => OPEN , clkdv => OPEN , LOCKED => s_dll_locked_ext );
obuf_i1 : OBUF PORT MAP ( I => s_clk_dllx2_ext , O => s_cko_54MHz );
cko_54MHz_1 s_clk_in_ibuf , D => s_dll_locked_ext , Q => s_dll_locked_ext_dly , CE => s_logic1 , A3 => s_read_addr(3) , A2 => s_read_addr(2) , A1 => s_read_addr(1) , A0 => s_read_addr(0) );
s_dll_locked_ext_dly_inv s_clk_a_out , CLKFB => s_clk_108_ibuf , RST => s_dll_locked_ext_dly_inv , CLK2X => OPEN , clk0 => s_clk_dllx4_int , clk90 => OPEN , clk180 => OPEN , clk270 => OPEN , clkdv => OPEN , LOCKED => s_dll_locked_108int );
obuf1 : OBUF PORT MAP ( I => s_clk_dllx4_int , O => s_clk_108_out );
cko_54MHz_2 s_op_dlls_locked_extd , CE => s_logic1 , A3 => s_read_addr(3) , A2 => s_read_addr(2) , A1 => s_read_addr(1) , A0 => s_read_addr(0) );
s_read_addr '1' ) ;
ExpressIP_pipe_srl16_1_i3 : srl16e PORT MAP ( CLK => s_clk_in_ibuf , D => s_op_dlls_locked_extd , Q => s_op_dlls_locked_extdd , CE => s_logic1 , A3 => s_read_addr(3) , A2 => s_read_addr(2) , A1 => s_read_addr(1) , A0 => s_read_addr(0) );
op_dlls_locked_extd cki_capt , O => s_clk_capt_ibuf );
clkdll_i3 : CLKDLL PORT MAP ( CLKIN => s_clk_capt_ibuf , CLKFB => s_clk_capt_out , RST => s_ra_sys , CLK2X => OPEN , clk0 => s_clk_capt_int , clk90 => OPEN , clk180 => OPEN , clk270 => OPEN , clkdv => OPEN , LOCKED => s_dll_locked_capt );
bufg1 : BUFG PORT MAP ( I => s_clk_capt_int , O => s_clk_capt_out );
ckr_capt