Tristate Discussion

You can use it in any module. Just declare your signals inout. You can even use tri-state busses internal to avoid coding the MUXs. The synthesizers are smart enough to substitute the tri-state busses by MUXs. I've used this to define in one module which IO components are integrated for the processor only by component declarations.

Yes Quartus does fine. It has (or had) only a problem when you assigne the 'Z' value inside a clocked process. Better do it outside of a process with a concurrent statement.

Martin

It is at least possible to do in verilog with QII.

What I haven't figured out how to do is connect two inout lines together without a module in between.

I can rename an ordinary signal with an assign, but not an inout line. The verilog tran gate won't synthesize.

-- glen

Hi Martin,

thank you for your reply.

What do you mean with "Just declare your signals inout" ?

I have a sub-module called "sdram.ctrl.vhd" which has an inout port "DQ[15..0]". The tristate description is within that module. On my top level file I instantiate the module with

i4 : sdram_ctrl port map ( ... DQ => top_signal_dq, ... ); "top_signal_dq" is of STD_LOGIC_VECTOR(15 DOWNTO 0).

In the top level file I make then the assignment:

DQ_TOP DQ_TOP, ... );

Kind Regards Andrés

...

That way is fine. Try it out and Quartus will not complain.

Martin

(snip)

At least in verilog connecting inout ports directly to the submodule works. I have not found out how to connect two inout ports within a module (whether connected to a submodule or not). Assignment is not bidirectional, so you can't do that. The verilog TRAN gate is not synthesizable, but should work if it was.

-- glen