Problem of module design

Nov 25, 2004 0 Replies

Hello, all



I am now doing a program to test my module design and I use ISE6.2 under windows XP.



I synthesize the top-level design and modules with XST(under windows mode). When synthesizing top-level file, I selected "Add I/O buffer", and deselecting it when synthesizing modules file. Then I use command mode to implement them.



It looks o.k. when I do " ngdbuild ?modular initial?." And "ngdbuild ?modular module ?active module ?." But when I use map command to this active module A, the following message appears.


---Writing file test_map.ngm?



---Waring : Line numbe 0: Found and unexpected XMODULE_CELLTYPE property on frag T_b1.



?
?

?-(The same warings to all top-level ports)


---Runing directed packing?


---Running delay-based LUT packing?



Running related packing?


---FATAL_ERROR : Ncd : nc_isetfactory_imp.c:738:1.22.4.1 ? Active module interfaces are missing. Process will terminate.


And there is the same problem when I doing the previous xapp290 example under the same situation.


Another question is I add some constrains attribute in VHDL code



(i.e. attribute iob : string;



attribute iob of LED_A_out : signal is "true";) but it dose nothing.


Could anyone give me some ideas about these problems? Thank you very much.


gray_i


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