Hi John, "But it's never good design practice to have tristates with multiple sources; "
I disagree with your opinion.
Tristate gates are used everywhere in an ASIC chip with no exception of FPGA. BLOCK RAM in Xilinx chip has to use tristate to get the selected data to output.
In my opinion, there are two types of tristate buses:
- Passive. It works well for interrupt system. If one of sources is to assert, it pulls down the bus. If it is to deassert, tristate the output and leave the bus to return high state by a pullup. It cannot be used for fast data transactions.
- Active. It works well for any multiple mutually exclusive sources to drive a data bus. The example is BLOCK RAM in Xilinx FPGA. In a normal FPGA design, the tristate bus can be safely used for the last stage of data output. This type of tristate buses is active because only one source drives the data bus at each clock, either high or low, there is no limit on its driving data. In my many designs, tristate data bus for the last stage of data outputs is much better than combinational logic. I will do a comparison between a tristate bus and its logic equilance for Xilinx chip to see if there is any impact on the performance. I have been always using tristate bus for my last stage of data outputs.
By the way, there is an patent from Xilinx: 5,677,638 "High Speed Tristate Bus with Multiplexers for Selecting Bus Driver". It deals with what you want to know. One trick is you always can find the most secret or core technology of Xilinx by reading their patents. All patents must meet a requirement that can be implemented by people in the art. We always belong to the people in the art.
In my opinion, there are many smart and brand new ideas imbedded in the
1100 patents of Xilinx that give you many lessons, teaching and experiences that couldn't get from college or textbooks, but they also expose many points that can be further improved.
Altela seems to adopt another type of strategies and tries to keep its secrets as commercial ones. Recently Alterla has gotten few patents. I don't know why.
Weng