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Asynchronous signals and simulation

I'm simulating a design where a number of external signals is asynchronous in respect to the main FPGA clock. The device targeted is Virtex2 and I'm using ISE and Modelsim XE. During timing simulation, asynchronous signals often cause setup/hold time violations when synchronized to the main clock. I know about ASYNC_REG constraint that makes that no 'X' propagates through the desing when timing violation happens. However the timing violations are still reported in Modelsim, and because there are many of them it is difficult to spot the messages that may be really important. Is there any way to switch off reporting setup/hold timing warnings for a particular flip/flop? Any other ideas?

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Regards
RobertP.
Reply to
RobertP
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Consider pre-synchronizing the testbench stimulus for the purposes of a functional simulation.

-- Mike Treseler

Reply to
Mike Treseler

Robert, I have named asynchronous flip-flops with a unique prefix that helps identify it as a flop where timing violations are expected. One could filter out references to this from a timing report to get a more concise report. Another. perhaps more drastic option is to find the async instances in the sdf file and change the setup and hold to "0.0". One has to be careful not to shoot oneself in the foot when doing these things.

Newman

Reply to
newman5382

You can use the tcheck_set command in modelsim to remove timing checks from the synchronising elements. You can remove one single check or all of them. See the example below. Note that if you try to remove nonexisting check or element Modelsim sometimes crashes :)

tcheck_set /dut_top/dut_inst/foobar1 "( PERIOD (posedge CLK) )" OFF tcheck_set /dut_top/dut_inst/foobar2_reg OFF

--Kim

Reply to
Kim Enkovaara

Looks like a goog solution, but unfortunately this command is available in Modelsim SE and not in Modelsim PE nor Modelsim SE that we have in the office.

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Regards
RobertP.
Reply to
RobertP

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