Hello,
A colleague of mine is simulating a post-routed with back-annotated FPGA design for an Actel chip on Modelsim. He is getting a number (1000's) of glitch warnings related to what seems to be combinatorial logic that is part of a counter and or muxes which is registered on the outputs anyway. None of the glitches are visible on the input or outputs but is on the internal nets. Can we safely ignore these warnings or better yet turn them off with -no_glitch option?
Thanks in advance.
Salman