Hi all,
Has anybody used the hypertransport lite reference design provided by Xilinx.
I cant seem to get it to work. I unzipped the design and changed the synthesis tool to xst.
The VHDl design dosent synthesize and the verilog version synthesizes but when the simulator is run it gives a message " Error: received data does not match expected data".
Does anybody know the solution to this. Do any other settings need to be made?
thanks, Aniket