Hello all.
I am new to VHDL and I was looking for help crating a 2D array of std_logic_vectors and initilizing it.
i think i got the first part correct, as there were no errors compiling and syntesizing in ISE.
my sytax is type ARR is array (1 downto 0, 1 downto 0) of std_logic_vector(3 downto
0);signal my_array : ARR;
now i wanted to initilize the data i used my_array(0,0)