2D array of std_logic_vector in VHDL

Hello all.

I am new to VHDL and I was looking for help crating a 2D array of std_logic_vectors and initilizing it.

i think i got the first part correct, as there were no errors compiling and syntesizing in ISE.

my sytax is type ARR is array (1 downto 0, 1 downto 0) of std_logic_vector(3 downto


signal my_array : ARR;

now i wanted to initilize the data i used my_array(0,0)

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If you use an array of arrays of SLV, you can say:

my_array (others => (others => '0')));

I'm not sure if 'others' works with two dimmensional arrays, but I always use arrays of arrays because then you can access my_array(i) [=array of slv], or my_array(i)(j) [=slv], or my_array(i)(j)(k) [=sl].


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