As a part of a larger project I'm currently designing a small module that will take 13 bits as an input and will output the commonest value in the input at its output. Ie: it will output a 1 if there are 7 or more bits set in the input, and will output a 0 otherwise. The design is beeing done in VHDL.
My first attempt was to write a process with for loop that counted the number of bits set in a variable and then setted the output bit accordingly. The problem with this approach was that the synthesizer inferred 12 4-bit adders and so the design was way too big and way too slow.
After some other failed attempts I stumbled upon this solution:
library IEEE; use IEEE.std_logic_1164.all;
entity bit_decide is port ( Bits_in : in std_logic_vector (12 downto 0); Bit_out : out std_logic ); end entity bit_decide;
architecture bit_decide_arc of bit_decide is
type partcnt_t is array (3 downto 0) of integer range 0 to 3; type partcnt2_t is array (1 downto 0) of integer range 0 to 6;
signal partial_count : partcnt_t; signal partial_count2 : partcnt2_t; signal bits_set_count : integer range 0 to 13;
begin
with Bits_in (2 downto 0) select partial_count(0)