attribute +generate statement

Hi, I'm trying to used the primitive ROM128X1 in my design and I want to initialise the attribute INIT of this primitive. This is working fine when I use only one primitive like :

---------------------------- architecture ... component ROM128X1  -- synthesis translate_off  generic (INIT : bit_vector := X"128");  -- synthesis translate_on  port (     O : out std_ulogic;     A0 : in std_ulogic;     A1 : in std_ulogic;     A2 : in std_ulogic;     A3 : in std_ulogic;     A4 : in std_ulogic;     A5 : in std_ulogic;     A6 : in std_ulogic  );  end component; attribute INIT : string; attribute INIT of U : label is ".."; begin     U : ROM128X1     port map(         O => data_out,         A0 => addr_in(0),         A1 => addr_in(1),         A2 => addr_in(2),         A3 => addr_in(3),         A4 => addr_in(4),         A5 => addr_in(5),         A6 => addr_in(6)     ); end;

---------------------------- but in the case I used a generate statement like : ---------------------------- begin     t : for i in 0 to 1 generate     U : ROM128X1     port map(         O => data_out(i),

        A0 => addr_in(0),         A1 => addr_in(1),         A2 => addr_in(2),         A3 => addr_in(3),         A4 => addr_in(4),         A5 => addr_in(5),         A6 => addr_in(6)     );     end generate; end;

--------------------------- what name of instance do I have to use to declare the attributes INIT. Thanks

Reply to
chris
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Something like U_0 and U_1, but I believe it depends on your synthesis tool. Check your synthesis output for the correct labels.

---------------------------- architecture ... component ROM128X1 -- synthesis translate_off generic (INIT : bit_vector := X"128"); -- synthesis translate_on port ( O : out std_ulogic; A0 : in std_ulogic; A1 : in std_ulogic; A2 : in std_ulogic; A3 : in std_ulogic; A4 : in std_ulogic; A5 : in std_ulogic; A6 : in std_ulogic ); end component; attribute INIT : string; attribute INIT of U : label is ".."; begin U : ROM128X1 port map( O => data_out, A0 => addr_in(0), A1 => addr_in(1), A2 => addr_in(2), A3 => addr_in(3), A4 => addr_in(4), A5 => addr_in(5), A6 => addr_in(6) ); end;

---------------------------- but in the case I used a generate statement like :

---------------------------- begin t : for i in 0 to 1 generate U : ROM128X1 port map( O => data_out(i), A0 => addr_in(0), A1 => addr_in(1), A2 => addr_in(2), A3 => addr_in(3), A4 => addr_in(4), A5 => addr_in(5), A6 => addr_in(6) ); end generate; end;

--------------------------- what name of instance do I have to use to declare the attributes INIT. Thanks

Reply to
Barry Brown

Hi

It's easier to embed the attribute inside the generate and assign the attribute value using some kind of function to make the code portable. Something like

t: for i in 0 to 1 generate attribute INIT of U: label is rom_init_values(i); begin U: ROM128X1 port map ( xxxx ); end generate;

where you've previously declared a constant array of init values for your ROMs. You can even put that constant array inside the generate, just before the attribute line

Best regards Francisco Rodriguez

"Barry Brown" escribió en el mensaje news: snipped-for-privacy@cswreg.cos.agilent.com...

tool.

Reply to
Francisco Rodriguez

the naming of elements built by a generate statement is not specified by the LRM, and is not consistent from tool to tool. To make it portable, as well as easier on yourself, put the attribute in the generate statement declaration rather than outside. Also, you'll need to specify the value for the generic with a generic map so that simulation matches the hardware:

----------------------------

attribute INIT of U:label is "..";

generic map( INIT => "...")

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

401/884-7930 Fax 401/884-7950 email snipped-for-privacy@andraka.com
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Reply to
Ray Andraka

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