I encountered problems synthesizing following VHDL-code with Altera Quartus 5.1. Although simulation with ModelSim was OK, the design in the FPGA did not work correct.
if ( (x - leftborder(resolution) + BlockCopyPixel > 0) then ...
where x : integer range -19 to 514; --So x can be negative leftborder(resolution): integer range 0 to 7; BlockCopyPixel : integer range 0 to 23;
After tracing my design with SignalTap I found out that the if-test did not work as expected when x was negative.
It worked as intended when I changed it to: temp:= resize(to_signed(x,12) - to_signed(leftborder(resolution),12) + to_signed(BlockCopyPixel,12),12); if (temp > to_signed(0,12)) then ...
This bug was very hard to trace. Is working with ranged integer types dangerous or is this a bug in Quartus?
Kind regards, Hendrik.