Quartus II and Synthesis

Do you have a question? Post it now! No Registration Necessary

Translate This Thread From English to

Threaded View
Any advice please.

I am creating a parallel uP interface to my fpga and i have separate
'processes' for the read and write functions.  My question is : Will
quartus synthesise separate address decoders - one for the read and
one for the write, or is it 'clever' enough to munge the two together
in the same decoder when synthesising ? (not sure of the tech term but
is this resource sharing ?)
Any help will be much appreciated

Re: Quartus II and Synthesis
Quoted text here. Click to load it

Unless you need to do both at once,
consider procedures in the same process.

Quoted text here. Click to load it

Only if your code tells it to.

Quoted text here. Click to load it

Learn simulation.

      -- Mike Treseler

Re: Quartus II and Synthesis
snipped-for-privacy@yahoo.co.uk (JohhnyNorthener) wrote in message
Quoted text here. Click to load it

Quartus II 4.0 (which is in manufacturing as I write this) has this
option. It is called Auto Resource Sharing and needs to be turned on.
The default value is off. This option is accessed through the
Assignment->Settings->Analysis & Synthesis Settings->More Settings

The help for this option says:
"Allows the Compiler to share hardware resources among many similar,
but mutually exclusive, operations in your HDL source code. If you
enable this option, the Compiler will merge compatible addition,
subtraction, and multiplication operations. By merging operations,
this may reduce the area required by your design. Because resource
sharing introduces extra muxing and control logic on each shared
resource, it may negatively impact the final fmax of your design."

- Subroto Datta
Altera Corp.

Re: Quartus II and Synthesis
Thanks for the response guys

Site Timeline