I am a newbie with this FPGA stuff, but I'm having to use a Stratix II design to develop some software until they can get me a chip that works. So please forgive me if I misuse terms or appear ignorant. I am! ;)
In this design, we have memory images in .hex files that are picked up by the Quartus compiler and placed onto the Stratix board during the .sof file download. I can also download these images individually within the In-System Memory Content Editor. The problem that I'm seeing is that a location in one of the images is not what is in that .hex file.
Is there a way to tear down the .sof file so that I can see if the problem is happening during the compiler process or if it is happening during or after the download?
We are using Quartus II (5.0 SP2 or 6.0 SP1) on Windows XP Home Edition (2002 SP2) within a Parallels (Build 1970) VM on an iMac 2GHz Intel Core Duo (OSX 10.4.8). The memory images and FPGA project files are stored in OSX and accessed over Parallels sharing with a mapped network drive. However, I have the same behavior if I move the entire folder over to the WinXP drive.
Has anyone else seen this type of problem?
DaR