Dear Sir or Madam,
I am trying to describe a module in VHDL which is capable of treating incoming parallel 16 bits (data rate 30MHz). An internal 90Mhz clock is used to nrzi-decode and to unstuff the 16bit-words. Apart from that the vector "gaps" (removed stuff bits) are bridged by shifting the adjacent bit positions up so that a complete 16bit word can be passed on to a next stage when all bit positions of the cleaned 16bit vector have a valid value. All this should be completed after 3 clock cylces (90MHz) so that the next
16bit-word (30MHz)can be handled.My question: (info: I use Altera QuartusII software)
I have written some VHDL code for that module. Because of an error message I do not know if the timing of >=90MHz is achieved. The error message occurs in the state "s_unstuff" of the state_machine when trying to define a loop border which is not static. Its value comes from the former state where the value is calculated. Is there a possibility to define such a loop (while-loop or for-loop) ? I have tried both: "while" and "for" but there always is the error message that constants have to be used. What can I do about that? Are there other alternatives?
Thank you for your help.
Regards Eva
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library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
entity Decode_destuff is port ( Reset : in std_logic; Clk : in std_logic; In_rec_enable : in std_logic; Data_in : in std_logic_vector(15 downto 0); Out_flag : out std_logic; Pos1 : out std_logic_vector(4 downto 0); Pos2 : out std_logic_vector(4 downto 0); Data_cleaned : out std_logic_vector(15 downto 0) ); end Decode_destuff;
architecture behavior of Decode_destuff is
signal l_data_in_reg : std_logic_vector(15 downto 0); signal l_unstuff_buffer : std_logic_vector(15 downto 0);
signal l_decoded_data : std_logic_vector(15 downto 0); signal l_bit_position1 : integer range 0 to 15; signal l_bit_position2 : integer range 0 to 15; signal l_flag : std_logic; signal l_bit_count : integer range 0 to 15; signal l_mark_border : std_logic; signal l_position1_valid : std_logic; signal l_position2_valid : std_logic;
type type_treat is ( s_ini, s_decode, s_unstuff, s_wait ); signal state_treat : type_treat;
begin
Data_cleaned