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modelsim crashs with large ram simulation model

I 'd like to simulate my design with a memory simulation model. The vhdl for memory model is like this:

------------------------------------------------------------------------------- constant weight_L : integer := 16; constant mean_L : integer := 28; constant variance_L : integer := 24;

type Gauss_parameters is record weight : std_logic_vector(weight_L-1 downto 0); mean1 : std_logic_vector(mean_L-1 downto 0); mean2 : std_logic_vector(mean_L-1 downto 0); mean3 : std_logic_vector(mean_L-1 downto 0); variance : std_logic_vector(variance_L-1 downto 0); end record; type ram_data_type is array (0 to 352*288*9) of Gauss_parameters; signal ram_data : ram_data_type;

-------------------------------------------------------------------------------

whenever I use modelsim to start simulation, the memory uesed by modelsim will exceed 4G memory, and modelsim crashs. I am using Sun server with 16G RAM. Can anyone tell me whether it is the problem of my design or the bug with modelsim. Is there another way to write memory simulation model that uses much less memory during simulation?

/hongtu

Reply to
Hongtu
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If the array is sparse you could dynamically reserve the memory. Also use variable instead of signal for the array, because signal has much more state and consumes more memory.

You could also use bit* types because they have less states than std_logic type.

And if you want to use 64b modelsim you need to install that separately and set the scripts accordingly. 64b modelsim is not normally used, because it is ~25% slower than the 32b version.

--Kim

Reply to
Kim Enkovaara

0);

Yikes, a signal!

Use a variable (in a process) instead. A signal takes much more memory because it has to drag along a complete event queue and all its attributes. A variable is much more light weight (up to a factor of ten, if I'm not mistaken).

Still, the amount of memory will be quite large. Your array will take

113135616 (107M) std_logic bits. Using naturals for the record members will improve this.

Paul.

Reply to
Paul Uiterlinden

Thank you guys! when I change the signal to variables, everything works smoothly.

/hongtu

Reply to
Hongtu

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