ModelSim 6.0 v 5.7 Can't read file

When I upgrade(?) to ISE 7.1.4 and ModelSim 6.0 I find my testbenches can not read binary files. Is this a technical problem or a downgrade on ModelSIM XE free offering. Note this is a binary file read not a textio file read which, according to the manual, is still available.

Brad Smallridge Ai Vision

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Brad Smallridge
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Try downloading and running this example and see if the resulting ./char_file.bin matches the source comments.

formatting link

vcom char_file.vhd vsim -c char_file -do "run 1";

It works fine for me using Modelsim 6.1c.

-- Mike Treseler

Reply to
Mike Treseler

Yeah. That runs. Funny.

Here's my code:

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL;

ENTITY tb IS END tb;

ARCHITECTURE behavior OF tb IS

component top port ( clk : in std_logic; reset : in std_logic; vframe_in : in std_logic; -- 1 when the image is valid vline_in : in std_logic; -- 1 when the line is valid vblob : out std_logic; vin : in std_logic_vector(7 downto 0); vred : out std_logic_vector(7 downto 0); vgreen : out std_logic_vector(7 downto 0); vblue : out std_logic_vector(7 downto 0) ); end component;

signal clk : std_logic; signal reset : std_logic; signal vframe_in : std_logic; signal vline_in : std_logic;

-- signal vline_out : std_logic; signal vblob : std_logic; signal vin : std_logic_vector(7 downto 0); signal vred : std_logic_vector(7 downto 0); signal vgreen : std_logic_vector(7 downto 0); signal vblue : std_logic_vector(7 downto 0);

constant start_recording_row_delay : integer := 2; constant start_recording_col_delay : integer := 8;

constant clkperiod : time := 20 ns; constant line_synchs : integer := 4;

type char_file is file of character; -- one byte each

file my_file : char_file; file my_file2 : char_file;

constant file_name : string := "infile.bmp"; constant file_name2 : string := "outfile.bmp";

type int_array is array(53 downto 0) of integer; type char_array is array(53 downto 0) of character;

signal bmp_char:char_array; signal start_recording : std_logic; signal row_counter : std_logic_vector(15 downto 0);

function bmp_function( bmp_header:int_array; bmp_start, bmp_data_size : integer ) return integer is variable result : integer; variable multiplier : integer; variable bmp_pointer : integer; begin result := 0; multiplier := 1; bmp_pointer := bmp_start; for i in 0 to (bmp_data_size-1) loop result := result + multiplier*bmp_header(bmp_pointer); multiplier := multiplier*256; bmp_pointer := bmp_pointer+1; end loop;

-- result_vector := std_logic_vector(to_unsigned(result,result_vector'length)); return result; end function bmp_function;

--BMP Header signal file_size : std_logic_vector(31 downto 0); signal reserved1 : std_logic_vector(31 downto 0); signal reserved2 : std_logic_vector(31 downto 0); signal offset : std_logic_vector(31 downto 0);

--BMP Info signal size : std_logic_vector(31 downto 0); signal width : std_logic_vector(31 downto 0); signal height : std_logic_vector(31 downto 0); signal planes : std_logic_vector(31 downto 0); signal bits : std_logic_vector(31 downto 0); signal compression : std_logic_vector(31 downto 0); signal imagesize : std_logic_vector(31 downto 0); signal xresolution : std_logic_vector(31 downto 0); signal yresolution : std_logic_vector(31 downto 0); signal ncolors : std_logic_vector(31 downto 0); signal importantcolors : std_logic_vector(31 downto 0);

BEGIN

uut: top PORT MAP( clk => clk, reset => reset, vframe_in => vframe_in,

-- vframe_out => vframe_out, vline_in => vline_in,

-- vline_out => vline_out, vblob => vblob, vin => vin, vred => vred, vgreen => vgreen, vblue => vblue );

clock_process: process begin clock_loop: loop clk

Reply to
Brad Smallridge

Modelsim compiles and elaborates your tb ok up to the uut. tb probably needs some code trace / debug to find the problem. Good luck.

-- Mike Treseler

PS: I would just covert the bmp file to a vhdl constant array using a script [bash|perl|python|etc].

______________________________

76 Sun Mar 12 /evtfs/home/tres/vhdl/play> vsim -c tb Reading /flip/usr1/modeltech/tcl/vsim/pref.tcl

# // ModelSim SE 6.1c Nov 17 2005 Linux 2.6.5-7.201-smp # Loading /flip/usr1/modeltech/linux/../std.standard # Loading /flip/usr1/modeltech/linux/../ieee.std_logic_1164(body) # Loading /flip/usr1/modeltech/linux/../ieee.numeric_std(body) # Loading work.tb(behavior) # ** Warning: (vsim-3473) Component instance "uut : top" is not bound. # Time: 0 ns Iteration: 0 Region: /tb File: tb.vhd VSIM 1> run 1 # ** Failure: bmp file not 24 bit type # Time: 0 ns Iteration: 0 Process: /tb/tb File: tb.vhd # Break at tb.vhd line 311 # Stopped at tb.vhd line 311

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Mike Treseler

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