What does this mean?
Maximum output required time after clock: 6.060ns
Is this the time required for the clock edge at the pin to some register inside the fpga or from the edge to some signal at an output pin or something else?
b r a d
Howdy Brad,
What is the name of the timing parameter that you are referring to, and what vendor/part/speed does it apply to? The name typically looks like Tcksomething. The terms "output" and "required" normally don't go together in timing parameters that I can think of.
If you are using Xilinx, the online interactive datasheets usually provide a description of what the parameter means:
Good luck,
Marc
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