Hi,
As you know Xilinx does not specify clock to output MINIMUM time of their devices. They only specify clock to output MAX time. The Tco MIN is used in calculating hold margin when there are devices on the bus with positive hold time requirement. What is your experiance, how to deal with this situation, how to simulate best case?
Regards Wojtek
IIRC there was an earlier thread on this, and I think the consensus was to use one quarter of the MAX time. [.. but the IC vendors really _should_ include this in the data sheets...]
-jg
Jim Granville napisal(a):
Thanks, I found this thread. The most pesimistic approach is: Tickofdcm(min) = Tickofdcm(max) - 3/4Tiockp(max) - 2xCLKOUT_PER_JITT0 -
2xCLKIN_CLKFB_PHASE.I only wonder why period jitter and phase error are doubled in this equation?
WJ
Are the jitter/phase specs RMS? If so, this probably tries to account for the crest factor (ratio of peak to RMS).
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