SDRAM bus termination

Hello folks,

I am concerned with whether or not to terminate my SDRAM bus and whether or not to add series resistors. The RAM will be very close to the IC driving it:

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(the through-hole connector is for reference only). As you can see, the trace lengths are very small, but the tight spacing also means that there's no room for resistor packs without having to use a larger PCB size.

The SDRAM is 100MHz. Any advice is appreciated!

Regards, Rafe

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There are documents which describe how to layout a DIMM. The PC-100 specification. I think you can get it for free. IIRC, it was an Intel spec and now it is a jedec spec.

If you have an array of SDRAM chips in parallel, then you should probably follow the guidelines of the jedec specification. If you just have one chip, your signal integrity will probably be OK without any termination, especially if the driver has variable strengths. But you will have to examine the timing situation very carefully.

Perhaps the ideal thing would be to simulate using the ibis models.

Oh, and I would definitely put termination on the clock. Put a resistor near the driver and a cap near the load. You can jumper the resistor, and leave the cap out at first, but if you don't pass FCC class A, you at least have some easy tweaks to try. This also allows you to tweak the timing a bit by slowing down the rising edge of the clock.


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