I was experimenting a coregen generated FFT module. How come the slice utilization jump 6 fold from the synthesis report to map report? XST does not just synthesis the logic into generic logics, it synthesize the logic to target resources, right? What I am saying is that if I change the target device, the # of slice used would change if the architecture of the slice is different between these two devices. So why there is such a big change in the # of slice used (and other resource for that matter) between MAP report and synthesis report. I am definitely a newbie, so please bear with me.
Thanks, Charles