xapp 482 and add custom function

Hi, there

I am a newbie in fpga area. I have a question about xps 6.3 mapper I am creating a project file based on xapp 482 which has a bootloader function and one can load application code( in C ) to the SRAM.

From the hardware aspect, I wanna add custom function using FSL.

But as XPS goes through the xflow. It stopped at the map phase. It has two suggestions came from the tool.

Now the questions

  1. I dont know where can change this parameter "-r" and
  2. if the "-r" doesnot work, must I change to another board?

actually the user function core has only 1 int array with 40 elements as input, and 1 int array with 1 element as output.

can somebody tell me why the size turn to so big. coz i checked the usage of "Number of 4 input LUTs:" without using the user function is 50%.

############################# Release 6.3i Map G.38 Xilinx Mapping Report File for Design 'system'

Design Information

------------------ Command Line : map -o system_map.ncd -pr b system.ngd system.pcf Target Device : 3s200 Target Package : ft256 Target Speed : -4 Mapper Version : spartan3 -- $Revision: 1.16.8.2 $ Mapped Date : Mon Jul 04 00:44:16 2005

Design Summary

-------------- Number of errors: 0 Number of warnings: 71 Logic Utilization: Number of Slice Flip Flops: 1,521 out of 3,840 39% Number of 4 input LUTs: 1,924 out of 3,840 50%

Number of RPM macros: 5 Total equivalent gate count for design: 130,923 Additional JTAG gate count for IOBs: 3,744

project with user function

######################################### ERROR:Pack:18 - The design is too large for the given device and package.

If the slice count exceeds device resources you might try to disable register ordering (-r). Also if your design contains AREA_GROUPs, you may be able to improve density by adding COMPRESSION to your AREA_GROUPs if you haven't done so already.

NOTE: An NCD file will still be generated to allow you to examine the mapped design. This file is intended for evaluation use only, and will not process successfully through PAR.

This mapped NCD file can be used to evaluate how the design's logic has been mapped into FPGA logic resources. It can also be used to analyze preliminary, logic-level (pre-route) timing with one of the Xilinx static timing analysis tools (TRCE or Timing Analyzer).

Design Summary: Number of errors: 1 Number of warnings: 75 Logic Utilization: Number of Slice Flip Flops: 1,793 out of 3,840 46% Number of 4 input LUTs: 11,925 out of 3,840 310% (OVERMAPPED) Logic Distribution: Number of occupied Slices: 6,580 out of

1,920 342% (OVERMAPPED) Number of Slices containing only related logic: 6,123 out of 6,580 93% Number of Slices containing unrelated logic: 457 out of 6,580 6% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 12,929 out of 3,840 336% (OVERMAPPED) Number used as logic: 11,925 Number used as a route-thru: 579 Number used for Dual Port RAMs: 264 (Two LUTs used per Dual Port RAM) Number used as Shift registers: 161 Number of bonded IOBs: 78 out of 173 45% IOB Flip Flops: 74 Number of Block RAMs: 1 out of 12 8% Number of MULT18X18s: 3 out of 12 25% Number of GCLKs: 2 out of 8 25% Number of BSCANs: 1 out of 1 100%

Number of RPM macros: 5 Total equivalent gate count for design: 226,883 Additional JTAG gate count for IOBs: 3,744 Peak Memory Usage: 163 MB

Thanks for any kinds of tips and helps

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