I am trying to fit this particular design. I run Synplify Pro to map the device. In Synplify, with mapping logic to atoms turned on, the design won't fit so I disable mapping logic to atoms and can get the design to fit (63 % of device) onto the device....see log file from synplify below.
However, when I try to place and route the device in Quartus III, it cannot fit. Quartus uses the same project directory as Synplify so it has access to all constraints and tcl files. Can anybody shed any light on this subject. I have used Synplify in conjunction with Quartus before and the resource useage results from both are nearly always about the same. Why the large discrepency ?
Do I manually need to read in some tcl files or have I forgotten to switch on a particular option in Quartus ?
As always, thanks for any help Bob
Found clock clk with period 33.3333ns
--------------------------------------- Resource Usage Report
Final cell packing will be performed by Max+plus II. Please select a Logic synthesis style of "FAST" in Max+plus II. The following resource values are estimates.
Design view:work.comms(comms_architecture) Selecting part ep20k1000efc33-1
Logic resources: 24440 ATOMs of 38400 (63%) Number of Nets: 190215 Number of Inputs: 1298480 Register bits: 14312 (4094 using enable) Latch bits: 8106 ESBs: 0 (0% of 160) I/O cells: 0
Details: AND2: 8298 INV1: 3879 MUX1: 5834 SYNLPM_LAT1: 16356 S_DFF: 10218 S_DFFE: 4113 XOR2: 291 apex20k_lcell: 77185 apex20k_lcell_ff: 19 false: 7 inv: 9189 true: 7
Number of Inputs on ATOMs: 1298480 Number of Nets: 190215
Writing .vqm output for Quartus Writing Cross reference file for Quartus to c:\comms_vhdl\rev_1\comms.xrf Mapper successful! Process took 7284.92 seconds realtime, 7284.92 seconds cputime