GL85 synthesizable code

http://tech-www.informatik.uni-hamburg.de/vhdl /

http://tech-www.informatik.uni-hamburg.de/vhdl/models/gl85/gl85.tar.gz
Note that code uses, bit and logic_vector as data types.
You can convert these to std_logic, and std_logic_vector!

-dasari

the original from hamburg vhdl is probably not fully working at
least there is one modified version that claims severl problems
beeing fixed

this modified version synthesis OK, see below:
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Writing NGDBUILD log file "i8085_c.bld"...
NGDBUILD done.
Completed process "Translate".
Started process "Map".

Using target part "2vp7ff672-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:         317 out of   9,856    3%
  Number of 4 input LUTs:           3,614 out of   9,856   36%
Logic Distribution:
    Number of occupied Slices:                        1,876 out of   4,928   38%
    Number of Slices containing only related logic:   1,876 out of   1,876  100%
    Number of Slices containing unrelated logic:          0 out of   1,876    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          3,622 out of   9,856   36%
      Number used as logic:                        3,614
      Number used as a route-thru:                     8

   Number of bonded IOBs:              45 out of     396   11%
      IOB Flip Flops:                                18
   Number of GCLKs:                     3 out of      16   18%

Total equivalent gate count for design:  25,801
Additional JTAG gate count for IOBs:  2,160
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http://simlab.eecs.tufts.edu/simlab/html/8085_mod.html

the report was for code downloaded from above link

antti