Hi all,
I came back from vacation yesterday, and full of ideas I started to work where I left before the holidays. The first thing that happens is that I can't map my design anymore. The vhdl is exactly the same as earlier, and the only difference in the map report is the lines regarding related and unrelated logic below:
Design Summary
-------------- Number of errors: 0 Number of warnings: 130 Logic Utilization: Number of Slice Flip Flops: 7,351 out of 21,504 34% Number of 4 input LUTs: 5,267 out of 21,504 24% Logic Distribution: Number of occupied Slices: 5,505 out of 10,752 51% Number of Slices containing only related logic: 5,505 out of
5,505 100% Number of Slices containing unrelated logic: 0 out of
5,505 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 6,045 out of 21,504 28% Number used as logic: 5,267 Number used as a route-thru: 310 Number used as Shift registers: 468
Number of bonded IOBs: 132 out of 456 28% IOB Flip Flops: 5 IOB Master Pads: 55 IOB Slave Pads: 55 IOB Dual-Data Rate Flops: 26 Number of Block RAMs: 42 out of 56 75% Number of MULT18X18s: 40 out of 56 71% Number of GCLKs: 5 out of 16 31% Number of DCMs: 1 out of 8 12% Number of BSCANs: 1 out of 1 100%
Number of RPM macros: 26 Total equivalent gate count for design: 3,057,923 Additional JTAG gate count for IOBs: 6,336 Peak Memory Usage: 266 MB
Following the design summary is a note regarding related logic.
In my old map report none of this related logic stuff is present. But I can't really understand why the mapper fails due to this since none of the logic is unrelated.
I am pretty sure that my code hasn't changed during my vacation. Does ISE know that there is a new version out and it wants me to upgrade? ;-)
Has anyone experienced this before?
Regards Johan