Hello, I am using a Xilinx Spartan-3 FPGA (XC3S200-4), and I am having difficulty mapping the Digital Clock Manager (DCM) output onto my clock net using a global buffer.
My intent is to take my external clock, input it into the DCM, and use the double frequency output, X2, to run my internal logic. I used the Xilinx Wizard to generate code for the DCM, and I have am instance of that DCM in my VHDL file. The Wizard does map the X2 output to a Global Buffer, BUFG, but when I assign that output to my clock net, it looks like it is on a local routing line.
Should I assign my clock net to another BUFG? This looks like a waste of resources. I should only have to use one Global Buffer for the X2 output. I have attached my VHDL code below. Thanks for the help.
Here is the instantiation in my code:
Inst_dcm_x2: dcm_x2 PORT MAP ( CLKIN_IN => clock, -- This is my external clock in RST_IN => rst_bar, CLKIN_IBUFG_OUT => open, CLK0_OUT => open, CLK2X_OUT => clk, -- I am trying to map the CLK2X_OUT to clk LOCKED_OUT => dcm_locked );
Here is the VHDL code the wizard generated:
entity dcm_x2 is port ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKIN_IBUFG_OUT : out std_logic; CLK0_OUT : out std_logic; CLK2X_OUT : out std_logic; LOCKED_OUT : out std_logic); end dcm_x2;
architecture BEHAVIORAL of dcm_x2 is signal CLKFB_IN : std_logic; signal CLKIN_IBUFG : std_logic; signal CLK0_BUF : std_logic; signal CLK2X_BUF : std_logic; signal GND_BIT : std_logic; begin GND_BIT CLK0_BUF, O=>CLKFB_IN);
CLK2X_BUFG_INST : BUFG port map (I=>CLK2X_BUF, O=>CLK2X_OUT); -- CLK2X_OUT is already assigned to a BUFG, how do I map this to 'clk'
DCM_INST : DCM generic map( CLK_FEEDBACK => "1X", CLKDV_DIVIDE => 2.0, CLKFX_DIVIDE => 1, CLKFX_MULTIPLY => 4, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 25.000, CLKOUT_PHASE_SHIFT => "NONE", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", DUTY_CYCLE_CORRECTION => TRUE, FACTORY_JF => x"8080", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map (CLKFB=>CLKFB_IN, CLKIN=>CLKIN_IBUFG, DSSEN=>GND_BIT, PSCLK=>GND_BIT, PSEN=>GND_BIT, PSINCDEC=>GND_BIT, RST=>RST_IN, CLKDV=>open, CLKFX=>open, CLKFX180=>open, CLK0=>CLK0_BUF, CLK2X=>CLK2X_BUF, CLK2X180=>open, CLK90=>open, CLK180=>open, CLK270=>open, LOCKED=>LOCKED_OUT, PSDONE=>open, STATUS=>open);
end BEHAVIORAL;