Variable Phase Shifting for VirtexII DCM

Hello, i have a problem with my dcm modules. By changing of frequency the clock-out phase gets also changed. So I have found a xapp from xilinx which may help me (Active Phase Alignment xapp268).

I have used this in my design, but i cant see some changes and shold be error free. Maybe somebody can see the mistake:

---------------------------------------------------------------------------=

-------------------- clk_bufg : bufg port map(i =3D> clkdcm, o =3D> clk); clkx4_bufg : bufg port map(i =3D> clkx4dcm, o =3D> clkx4); clkx4not_bufg : bufg port map(i =3D> clkx4notdcm, o =3D> clkx4not); clk_ibufg : ibufgds_lvpecl_33 port map(i =3D> clkin_p, iB =3D>

clkin_n, o =3D> clkint);

attribute DFS_FREQUENCY_MODE of dcm_clk : label is "HIGH"; attribute CLKOUT_PHASE_SHIFT of dcm_clk : label is "VARIABLE"; attribute PHASE_SHIFT of dcm_clk : label is "-255"; attribute CLKFX_DIVIDE of dcm_clk : label is dcm_clk_d; attribute CLKFX_MULTIPLY of dcm_clk : label is dcm_clk_m; attribute DUTY_CYCLE_CORRECTION of dcm_clk : label is "TRUE" ; attribute CLKDV_DIVIDE of dcm_clk : label is "4" ; attribute DLL_FREQUENCY_MODE of dcm_clk : label is "HIGH";

dcm_clk : dcm

--pragma translate_off generic map ( CLKFX_MULTIPLY =3D> dcm_clk_m_udsim, CLKFX_DIVIDE =3D> dcm_clk_d_udsim, CLKDV_DIVIDE =3D> 4.0, CLKOUT_PHASE_SHIFT =3D> "VARIABLE", PHASE_SHIFT =3D> 160)

--pragma translate_on port map ( clkin =3D> clkint, CLKFB =3D> clkx4, DSSEN =3D> low, PSINCDEC =3D> psincdec_tx, PSEN =3D> psen_tx, PSCLK =3D> psclk_tx, RST =3D> rx_dcm_lock_loss, CLK0 =3D> clkx4dcm, CLK90 =3D> open, clk180 =3D> clkx4notdcm, CLK270 =3D> open, CLK2X =3D> open, CLK2X180 =3D> open, CLKDV =3D> clkdcm, CLKFX =3D> open,

CLKFX180 =3D> open, LOCKED =3D> clk_locked, PSDONE =3D> psdone_tx, STATUS =3D> open); .=2E.. .=2E.. ph_shift_tx : phase_control_full_range port map( enable =3D> high, monclkin =3D> clkint, rxclkin =3D> clk, -- clk ctlclk =3D> clkdcm, lockedin =3D> clk_locked, rst =3D> tx_dcm_lock_loss, psdone =3D> psdone_tx, forceup =3D> low, forcedown =3D> low, dcm_div_2_used =3D> dcm_div_2_used, -- nope k =3D> const_offset, -- the same as for rx side lockedout =3D> dpclocked_tx, psincdec =3D> psincdec_tx, psen =3D> psen_tx, psclk =3D> psclk_tx, binout =3D> binout_tx);

-------------------------------------- The Design runs in DDR Mode, by changing of frequency from 300 MHz to

370 Mhz the phase jups ut to 180=B0.
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schirinboy
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