Hi, I am using a DCM block in my design. i generated it using XPS 7.1i and exporting it later to ISE7.1i to do synthesis. this is what I put in the system.mhs file
BEGIN dcm_module PARAMETER INSTANCE = dcm_module_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLKIN_PERIOD = 7.51879699 PARAMETER C_CLKDV_DIVIDE = 2.0 PARAMETER C_CLKIN_BUF = TRUE PARAMETER C_CLKDV_BUF = TRUE PORT CLKIN = dcm_clk_in_s PORT CLKDV = sys_clk_s PORT CLKFB = dcm_module_0_CLKFB PORT CLK0 = dcm_module_0_CLKFB END
this is the constraint that I put in the ucf file during synthesis by ISE
Net sys_clk_pin PERIOD = 7518 ps;
however although i specified it as clk freq as divide by 2, I get errors like the one below:
####################################################################### ##### Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation.
-----------------------------------------------------------------------
--------- Constraint | Requested | Actual | Logic | | | Levels
-----------------------------------------------------------------------
---------
- NET "bufgp_3/IBUFG" PERIOD = 7.518 ns HIG | 7.518ns | 9.825ns | 23 H 50% | | |
-----------------------------------------------------------------------
--------- ####################################################################### #####
which is strange since the period did not get multiplied by 2 as i mentioned in the system.mhs file. can anyone help? The funny thing is that when i generated the behavioral model and tried to verify it in modelsim, the clock coming out of the clkdv port is divided by 2. the XST somehow does not try to do that. why is not translated to the correct constraints? this is not what is being said in the xilinx man pages on how to constraint designs with DCM, that the ngdbuild will auto translate the constraints into the correct clk period * 2 as in for the case.
any advice? any one know if this is a bug.
Chris