A Virtex4 FPGA is mounted on a board which has a sleep mode to conserve battery power during periods of inactivity. Is it only necessary to keep the VCCaux power on to maintain the configuration memory, and all the other power inputs can be turned off?
Pomerado,
The Vcc_config must stay powered, the Vcc_aux must stay powered, and the Vccint must stay powered.
If any of these drops below their power on reset thresholds, the device erases all memory before trying to configure.
Vcco_config POR trip is ~ 0.5 to 0.75V Vcc_aux POR trip is ~1.3 to 1.8V Vccint POR trip is ~0.5 to 0.75V
I recommend that you may lower each supply only to what is specified in the recommended operating conditions table of the data sheet, and no less.
This, of course, after you place the design in a state where all clocks are disabled, IOs tristate, and just waiting for a signal on an IOB pin to wake up, and start processing from where it left off.
Table 4 is where you will find the min currents:
Aust> A Virtex4 FPGA is mounted on a board which has a sleep mode to conserve
The configuration user guide states that during the configuration memory input phase, the only I/O power that is needed is VCCo_0 (also known as VCCconfig), to drive the configuration data clock output.
"None of the I/O voltage supplies (VCCO), except VCCO_0 (VCC_CONFIG), need to be powered for Virtex-4 configuration in JTAG or serial modes."
VCCAUX Input Power-supply pins for auxiliary circuits VCCINT Input Power-supply pins for the internal core logic
VDRINT Data retention VCCINT voltage (below which configuration data might be lost)
0.9 V VDRI Data retention VCCAUX voltage (below which configuration data might be lost) 2.0 V Recommended operating conditions: VCCint 1.2V VCCaux 2.5V ICCINTQ Quiescent VCCINT supply current XC4VLX60 167 mA ICCAUXQ Quiescent VCCAUX supply current XC4VLX60 74 mAElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.