I have a working Spartan 3E design that I am porting to XC3S200AN. It has a handful of instantiated ODDR2s connected to instantiated OBUFDSes, such as the following:
serchan_gen : for chan in 0 to 3 generate -- here's the output DDR flop. u_oddr : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "ASYNC") port map ( Q => iDOut(chan), C0 => SerClk, C1 => SerClk_l, CE => iVcc, D0 => iD0(chan), D1 => iD1(chan), R => gReset, S => iGnd);
u_DOBUF : OBUFDS port map ( O => DOut_p(chan), OB => DOut_n(chan), I => iDOut(chan)); end generate serchan_gen;
If I assign the pins in my UCF as follows:
NET "DOut_n" LOC = D3 | IOSTANDARD = "LVDS_25"; NET "DOut_p" LOC = D4 | IOSTANDARD = "LVDS_25";
the mapper fails with the following inscrutable* messages:
ERROR:Pack:1107 - Unable to combine the following symbols into a single DIFFSTB component: PAD symbol "DOut_n" (Pad Signal = DOut_n) SlaveBuffer symbol "u_ddcltx/serchan_gen[0].u_DOBUF/ SLAVEBUF.DIFFOUT" (Output Signal = DOut_n) Each of the following constraints specifies an illegal physical site for a component of type DIFFSTB: Symbol "DOut_n" (LOC=D3 [Physical Site Type = DIFFSLR]) The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly. ERROR:Pack:1107 - Unable to combine the following symbols into a single DIFFMTB component: PAD symbol "DOut_p" (Pad Signal = DOut_p) BUFINV symbol "u_ddcltx/serchan_gen[0].u_DOBUF/OBUFDS" (Output Signal = DOut_p) Each of the following constraints specifies an illegal physical site for a component of type DIFFMTB: Symbol "DOut_p" (LOC=D4 [Physical Site Type = DIFFMLR]) The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly.
That's all very interesting, but WTF are DIFFMLR and DIFFMTB and DIFFSLR and DIFFSTB, anyways? Asking the great god Google for "Xilinx DIFFMLR" returns exactly zero results (well, maybe one, after this post is indexed). Nowhere in Xilinx' docs are these components mentioned.
Then I figure, OK, let's see what the tools do when one deletes the placement and I/O type constraints in the UCF.
Map completes, and the mapper assigns the IOB type DIFFMTB for all of the non-inverted LVDS output signals and it assigns the type DIFFSTB for all of the inverted LVDS output signals. Again, NOWHERE in the docs or on the Xilinx website are these components defined.
However, place and route bombs out with the following complaint:
ERROR:Place:866 - Not enough valid sites to place the following IOBs: IO Standard: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE (list of differential signals snipped)
This may be due to either an insufficient number of sites available on the device, too many prohibited sites, or incompatible I/O Standards locked or range constrained to I/O Banks with valid sites. This situation could possibly be resolved by one (or all) of the following actions: a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by using LOC or range constraints. b) Maximizing available I/O Banks resources for special IOBs by choosing lower capacity I/O Banks if possible. c) If applicable, decreasing the number of user prohibited sites or using a larger device.
This is all ridiculous because the device has an entire unused bank that it can use for these outputs.
So how does one use LVDS outputs on a Spartan 3AN device?
-a
- I say "inscrutable" because Xilinx apparently agrees with me:
"This valid error message is not very useful because of its generic nature; it is meant to describe a wide variety of conflicts between site types and the logical instances constrained to them. The key elements are as follows ..."