Spartan 3AN LVDS I/O

I have a working Spartan 3E design that I am porting to XC3S200AN. It has a handful of instantiated ODDR2s connected to instantiated OBUFDSes, such as the following:

serchan_gen : for chan in 0 to 3 generate -- here's the output DDR flop. u_oddr : ODDR2 generic map ( DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "ASYNC") port map ( Q => iDOut(chan), C0 => SerClk, C1 => SerClk_l, CE => iVcc, D0 => iD0(chan), D1 => iD1(chan), R => gReset, S => iGnd);

u_DOBUF : OBUFDS port map ( O => DOut_p(chan), OB => DOut_n(chan), I => iDOut(chan)); end generate serchan_gen;

If I assign the pins in my UCF as follows:

NET "DOut_n" LOC = D3 | IOSTANDARD = "LVDS_25"; NET "DOut_p" LOC = D4 | IOSTANDARD = "LVDS_25";

the mapper fails with the following inscrutable* messages:

ERROR:Pack:1107 - Unable to combine the following symbols into a single DIFFSTB component: PAD symbol "DOut_n" (Pad Signal = DOut_n) SlaveBuffer symbol "u_ddcltx/serchan_gen[0].u_DOBUF/ SLAVEBUF.DIFFOUT" (Output Signal = DOut_n) Each of the following constraints specifies an illegal physical site for a component of type DIFFSTB: Symbol "DOut_n" (LOC=D3 [Physical Site Type = DIFFSLR]) The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly. ERROR:Pack:1107 - Unable to combine the following symbols into a single DIFFMTB component: PAD symbol "DOut_p" (Pad Signal = DOut_p) BUFINV symbol "u_ddcltx/serchan_gen[0].u_DOBUF/OBUFDS" (Output Signal = DOut_p) Each of the following constraints specifies an illegal physical site for a component of type DIFFMTB: Symbol "DOut_p" (LOC=D4 [Physical Site Type = DIFFMLR]) The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly.

That's all very interesting, but WTF are DIFFMLR and DIFFMTB and DIFFSLR and DIFFSTB, anyways? Asking the great god Google for "Xilinx DIFFMLR" returns exactly zero results (well, maybe one, after this post is indexed). Nowhere in Xilinx' docs are these components mentioned.

Then I figure, OK, let's see what the tools do when one deletes the placement and I/O type constraints in the UCF.

Map completes, and the mapper assigns the IOB type DIFFMTB for all of the non-inverted LVDS output signals and it assigns the type DIFFSTB for all of the inverted LVDS output signals. Again, NOWHERE in the docs or on the Xilinx website are these components defined.

However, place and route bombs out with the following complaint:

ERROR:Place:866 - Not enough valid sites to place the following IOBs: IO Standard: Name = LVDS_25, VREF = NR, VCCO = 2.50, TERM = NONE (list of differential signals snipped)

This may be due to either an insufficient number of sites available on the device, too many prohibited sites, or incompatible I/O Standards locked or range constrained to I/O Banks with valid sites. This situation could possibly be resolved by one (or all) of the following actions: a) Grouping IOBs of similar standards into a minimum amount of I/O Banks by using LOC or range constraints. b) Maximizing available I/O Banks resources for special IOBs by choosing lower capacity I/O Banks if possible. c) If applicable, decreasing the number of user prohibited sites or using a larger device.

This is all ridiculous because the device has an entire unused bank that it can use for these outputs.

So how does one use LVDS outputs on a Spartan 3AN device?

-a

  • I say "inscrutable" because Xilinx apparently agrees with me:

"This valid error message is not very useful because of its generic nature; it is meant to describe a wide variety of conflicts between site types and the logical instances constrained to them. The key elements are as follows ..."

Reply to
Andy Peters
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Oh, yeah, because some people will ask. Yes, I did change the build target to XC3S200A (there's no specific callout for AN parts).

-a

Reply to
Andy Peters

Hi,

It could be that you are trying to put LVDS outputs on banks that don't support LVDS output. In Spartan-3A and Spartan-3AN, I believe you can only implement LVDS outputs on the top and bottom banks of the die.

For reference, a DIFFSTB is an IOB that is a DIFFerential Slave on the Top or Bottom of the die. A DIFFSLR, as you might imagine, is DIFFerential Slave on the Left or Right of the die. You also referenced some site types with an M in them instead of an S, those are Master site types. What the message is unsuccessfully trying to communicate is that you've got something that needs to be on a DIFF*TB site, but your location constraint is for a DIFF*LR site.

I cannot say for certain about the completely unconstrained I/O test you ran, but I suspect that the placer either wasn't able to figure out a solution to your design I/O requirements without some hints, or that you may have more LVDS outputs in your design than will fit on the top and bottom banks.

I hope that throws some light on it, Eric

Reply to
Eric Crabill

Regarding the LVDS output capability of the Spartan-3 Generation, check here:

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Look on page 334, Table 10-9.

Eric

Reply to
Eric Crabill

Arrrrgh, indeed, that is it.

I assigned my pinouts based on the PDF pinout from

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The pins I chose for my LVDS outputs were on Bank 3. The pins I chose were all labeled as I/O with names like L01N_3 and L01P_3. Naturally, I assumed that I/O mean I/O for the differential signaling as well as single-ended. But yes, the table in the user guide does indicate that

3AN devices allow LVDS outputs on banks 0 and 2 only. Perhaps a little note on the pinout page clarifying that would help.

I assumed that to be the case, but I was rather astonished that this isn't documented anywhere.

Actually, the problem is neither: it wasn't completely unconstrained I/ O. I left other pin assignments as is and unconstrained just the LVDS stuff. I designated bank 2 as 3.3V, so the tools couldn't assign LVDS_25 signals to it. Bank 0 was pretty full up with other things.

Project for Monday is to create a new pinout.

-a

Reply to
Andy Peters

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