simple delays

Apr 24, 2005 3 Replies

Rate this thread:

Amir Intisar 21 years ago

Hi, i am a newbee to FPGA design and i wanted to know how to add simple delay in my Spartan 3 XC3S200 FPGA. I have a 16 bit digital signal which comes from an imaging device(CCD) which may, for example represent the data on pixel 1. What i want to do is first send the pixel number to the computer, and then send the 16 bit data for that pixel to the computer. The output on the computer may look like something below,

1 - pixel no. 1
1345 - data for pixel 1

2 - pixel no. 2

2431 - data for pixel 2

1325

So do i have to send out the pixel number , then have a delay and send out the data for that pixel. Something like this??

out = pixel; #100 out = data_in;

Thanks !!!!!!!!

Vote

Hendra 21 years ago

The #sign delay is not synthesizable to the FPGA. But you still can implement a delay in different way. You can use a shift register or use a simple logic and a big counter that will send the input to the output once the counter reach a certain number. Note that in both cases, you must know in advance the speed of the clock before you can write the code to implement an accurate delay.

Hendra

Amir > Hi,

simple

send

Vote

amir.intisar 21 years ago

Hi Hendra, my clock is working at 50Mhz (20ns). I need a delay of

1micro second. Does this involve a counter that increments up to 50 (1*10us / 20*10ns = 50). Is this how you figure out the delay???

Thanks !!!!!!

Hendra wrote:

use

output

that

Vote

Peter Alfke 21 years ago

Yes, if tou really (??) need such a long delay, build a 6-bit counter. which takes 6 flipflops. Your 3S200 chip has >3600 flip-flops, so you can easily afford it. But I am still amazed about the need for such a long delay... Peter Alfke, Xilinx Applications

Vote

Join the Discussion

Have something to add? Share your thoughts — no account required.

Didn't find your answer?

Ask the community — no account required