Generating clock delays

Yes, synthesis ignores after statements generally.

That's basically the same problem as with "after".

That's the way to go - provided that your FPGA implements such a circuitry. DLLs are there for exactly such purposes.

Another alternative is to feed the clock through some normal circuitry. But you can't describe this in VHDL. Instead, you need to create a hard-macro that does nothing more than propagating the signal from input to output. Depending on the timing information you receive in the data sheets, you can calculate how often the signal needs to be feed through some LUTs or other parts. Although this method is not the very best one, it is working fine in many cases.

Regards, Mario

The usual approach for such a problem is to have a PLL. There are chips, such as the Cypress CY7B9911 clock skew buffer, or the Cypress CY7B9930 multi frequency PLL clock buffer.

Rene

Go re-read the synthesis tool documentation, especially the part about which VHDL language features are supported and which ones aren't.

"after" isn't. Spend a moment or two thinking about WHY. Hint: Think Hardware.

See above.

That's one way of doing it.

Perhaps rather than delaying the clock in such a manner, you need a higher-frequency master clock that you can use to clock your whole design. A simple state machine or whatever can be used to create clock enables at the appropriate time.

-a

Peter, out of curiosity, how many of these DLLs are in there ?

Rene

Peter Alfke wrote: