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Virtex4: Usign OSERDES + LVDS Deserializers

Hi

Has someone experience in using the OSERDES in combination with a commercial Deserializers like MAX9206/MAX9208 or SCAN921226 ? I was wondering whether it would be possible to meet the jitter requirements and thereby preventing that the deserializer's PLL unlocks. I can' find the right information for this in the Virtex-4 DC and Switching Characteristics. To generate e.g. 500Mb/s one needs to use a (500*12/10) / 2 MHz = 300MHz clock for the OSERDES. The OSERDES will use both edges of the clock to generate data in DDR mode. This will introduce some jitter and using a DCM with a multiplication factor of 5x for "CLK" will worsen the situation a lot. I guess it will be hard to prove the stability by means of static timing analysis.

Further, the OSERDES is not capable to generate packages of 12 bits that are required for most deserializers (1 start + 10 data + 1 stop bit). Probably this can be solved by some reshuffle module.

Finally, will the OSERDES width expansion run slower than one without? I couldn't find this information.

Roel

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Roel
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Here are the answers from our spreadsheet: Assuming 70% device utilization (which has an impact on jitter) and a

-11 speedgrade, a 100 MHz clock multiplied by 3, divided by 1 in FX mode generates a jitter of 29% or 987 ps. Duty-cycle distortion is a non-issue in Virtex-4, where it is very small. I do not have data for the jitter toleance of your receiving SERDESes.

Peter Alfke, Xilinx Applications

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Peter Alfke

I forgot: To send out 12 bits, you can send two successive words of 6 bits each.

Peter Alfke

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Peter Alfke

Thanks a lot for the fast feedback.

Maxim specifies for a bit rate of 600 Mbps (datarate 500Mbps) a tightened upper Limit of marginal jitter: 468 ps.

So it will require another way of clock generation. Probably I can use the CLK2X output a DCM, and use a 150Mhz external clock (150Mhz = CLKIN_FREQ_DLL_LF_MS_MAX ...). The total jitter will then be ±200 ps generate by the DCM. I can't find the duty-cycle distortion of the CLK2X output, the Virtex-4 Data Sheet is somewhat vague here. It's say in Table 36 of ds302.pdf that CLKOUT_DUTY_CYCLE_DLL = +- 150ppm for DLL outputs CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV. Further it says CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if DUTY_CYCLE_CORRECTION = TRUE). So for CLK2X, CLK2X180, and CLKDV the spec is +- 150ppm?

Then, in total the jitter will be 200+150=350ps, leaving 100ps margin for external imperfections, like the cable (will be short), seems to be ok.

Another option would be using a 300Mhz external LVDS oscillator, however that will cost as much a bunch of external serialisers.

Any other idea's?

Roel

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Roel

Oops, 150ppm is not 150ps but 0,5ps in the case of 300Mhz.

Roel

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Roel

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