routing delays (Xilinx)

Feb 24, 2005 1 Replies
J

Hallo,



is there a way to get delay-info on resource-basis? I'd like having the output of "XDL -report -pips" annotated with delay(functions). The purpose is to identify fast resources to ease up the design of macros such as those, XST tries to detect when syhthesising HDL and to gain my personal learning-curve about fpga-design (I don't see HDL-compilers do this=20 for me). I'm tired of writing just-a-few-slice-designs, wait a minute or two for the toolchain to print out a result, then modify the test, and again wait for the toolchain, and all this just to find out, what=20 leaving a carry-chain or whatever might cost.



Any ideas, how to get "XDL -report -pips" annotated with useful delay-estimates?



Gruss



Jan Bruns


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J

"Jan Bruns":

None?

Remember the purpose is to rapidly find rough estimtes for delays of small, clearly defined circuits within an fpga (so don't take that ASCII-file to serious).

I mean, it might be easy to classify wires by length and the number of pips directly on a wire. So it might even be easy to=20 find a roughly estimated phsical model of a net, given that driver's and line's (strength, capacitance per length-unit,...) properties (and maybe such of the inputs) are given.

So maybe some physical parameters about routing resources would do, for that ASCII-file.

Gruss

Jan Bruns

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