I am in the process of configuring a Block RAM in a Xilinx device with some constants. My implementation has some set of constants which are in a separate module and i want to intialize them in the RAM block. Inorder to do this i have created a Coregen of a single port memory and initialized with a .coe file, which was created using the memory editor. When i synthesized it i didn't find any Block RAM used. What would be the error?