Hi ,
I am in the process of configuring a Block RAM in a Xilinx device with some constants. My implementation has some set of constants which are in a separate module and i want to intialize them in the RAM block. Inorder to do this i have created a Coregen of a single port memory and initialized with a .coe file, which was created using the memory editor. When i synthesized it i didn't find any Block RAM used. What would be the error?
I want to add to the above statements that when i remove the comment line // synopsys translate_off and // synopsys translate_on i get an error during synthesis. I have listed the following error.
ERROR:HDLCompilers:87 - "D:/Xilinx/bin/nt/block_ram/constants.v" line
84 Could not find module/primitive 'BLKMEMSP_V6_1' ERROR: XST failed
Do you actually *use* the memory yet or are you just seeing if it initializes before you actually wire up the access to the BlockRAM?
Hi John,
It was a mistake on my side.I used the .v files generated by core gen. When i replaced the .v by .xco files it worked. Now i have a doubt of how to use the same for simulation. Can anyone give sugestions. I am using NC Verilog for simulation.
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