Hi People,
I have generated a duap port RAM using a Xilinx Core generator . Port A is 32 x 32 and Port B is 8 x 128
The 32 bit port , Port A , is interpreting the addresses in the row order
00 01 02 . . . 1FI had expected the 8 bit port to also interpret the addresses in the row order. I have done the simulation of the DPRAM and this was it responded as expected.
03 02 01 00 07 06 05 04 ......................... 7F 7E 7D 7CBut now comes the weird part . I implemented my design on a Xilinx Virtex - 2 Pro FPGA , the 8 bit port is interpreting the addresses in the column order ,. I have observed this using debug data as well as using Chip Scope Pro, i.e.
60 40 20 00 61 41 21 01 62 42 22 02 63 43 23 03 . 7F 5F 3F 1FAre there any synthesis constraints that can prevent this from happening . All the documents and application notes say that the 8 bit port also should be addressed in the row ordering fashion. Could any one suggest why I might be having this problem
Thank You Venu