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Buffers/Line drivers for 6pin JTAG?

Hello, everyone! I am trying to adapt Spartan 3 Starter Kit board as a standalone board for one of my projects. To download configuration to FPGA I want to use 6 pin serial JTAG. My question is: are there any strict specifications for the line driver that drives TDO line back to the PC? Any links addressing this issue would be very welcome!

TMS, TCK, TDI lines are driven by drivers inside the Xilinx parallel cable (which take the power from PC parallel port). They are Schmitt trigger type and quite fast: NL37WZ17 I was wondering if the TDO line buffer/driver needs to adhere to similar specifications? The board is to operate @ 3V.

Thank you!

Reply to
Telenochek
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I don't have the Starter Kit schematic to hand so this is a general statement. If the Spartan-3 is the last device in the chain then you should have sharpish edges on TDO as Spartan-3 has an active totem-pole o/p for TDO. This is not always the case as some Xilinx devices have an open drain drive and rely on a pullup for the high level. In the later edges can be slowish so schmitt is possibly better. That said Parallel Cable III uses

74xx125 drivers which are not schmitt.

John Adair Enterpoint Ltd. - Home of Raggedstone1. The $90 Spartan-3 Development Board.

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Reply to
John Adair

Thanks for your help! I think a 74LX1G126 will work with +/- 24mA sink & 10ns/V rise/fall time.

Reply to
Telenochek

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