RocketIO, where to start?

Hi Mikhael, If you have Xilinx CORE Generator installed, you can generate an Aurora module for your application. A single lane full-duplex Aurora module with a 4-byte streaming parallel interface will fit.

CORE Generator will give you the source code for the module, which you can integrate with your design. You'll need to provide a 140 Mhz reference clock to run the RocketIO; the module will provide a 70 Mhz clock derived from the reference clock for the parallel interface. The TX interface is a data port plus a ready signal and a data valid signal. The RX interface is a data port plus a data valid signal.

RocketIO uses Clock Data Recovery (CDR) which means the data you receive will be synchonized to a 70 Mhz clock recovered from the serial input. Unless you need the clocks on both devices to be exactly in phase, you wont need to provide the same clock to both FPGAs.

If this sounds like it might work for you, you should take a look at the Aurora Reference Design User Guide in the downloads section of the Xilinx Aurora lounge

-> Click the Access Lounge button for the Aurora Reference Design at the bottom of the page: the user guide is the second link.)

Regards, Nigel

MM wrote:

The Aurora module is a pretty good match for that, I would think. Yes it looks like a lot of info, mut mainly you will be concerned with TX_DIN and TX_WR (and perhaps TX_DST_RDY) on the write side, and RX_SRC_RDY and RX_DOUT on the receive side. They are simple handshaking signals which do exactly what the names imply, so the core is really easy to use. Read the section on clocking several times, though ;)

Unfortunately, getting the simulation up and running is a bit of a pain. Only Swift simulation models are provided for the RocketIO, and I think I spent most of a day researching these and getting them going in Modelsim, but they work fine after that. It was well worth the trouble; the simulation is pretty good fidelity.

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Hi Nigel,

Thanks for your help. When is the Aurora module going to be available for the V4 FX series? I know that even V4 MGBT user manual has not been released yet...

/Mikhail

Thanks Duane.

/Mikhail

The first Aurora code for Virtex 4 will be available in the first IPUpdate for ISE 7.1. You might also try talking to a Xilinx FAE in your area, since they can sometimes set you up with early access material.

Regards, Nigel

MM wrote:

On a different topic, what kind of error rate can I expect at 2.24 GB/s? Two FPGAs I am connecting with this link are on 2 separate PCBs (so called front and rear Compact PCI cards). The cards are connected with a 2mm Hard Metric "pass-through" connector. In other words there is a backplane or rather midplane between the cards, but there are no tracks, the signals pass directly through the vertical male connector pins sticking out on both sides of the plane, while each of the cards has a right angle female connector.

My problem is that I can't really have any errors at all... If that is not achieavable with RocketIO at the data rate I am interested in, then I guess I should look at other options. I noticed that there is a slower core in the Coregen, called High-Speed Data Serialization and Deserialization. I guess I could use 4 of them, one per each of the bytes in my packet and run them at

560 MHz. Would this be more reliable?

Thanks, /Mikhail

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Howdy Mikhail,

Unless you have something weird going on in your system, you should be able to achieve "error-free" links (better than 1E-12, let's say). Weird being something like noise on your MGT power or ground, or reference clock quality problems. With RocketIO, you trade fewer pins for a little more design complexity (due to the higher speeds). Thousands of people doing it (error free) though, so it works.

Have fun,

Marc

Thanks.

/Mikhail

MM,

A well designed link has 0 errors.

Yes, no errors.

No reason why you can not model this, and prove in simulation (hspice, nspice) that the link has more than enough margin to be error free.

I caused quite a stir when everyone wanted to publish an error rate of

1E-12 (basically one of the common specifications for XAUI, etc.) I said that since we have no errors in a properly designed link, the BER should be identically 0.

That is what we published.

My opinion: if there are errors, the link was not designed properly, and it is broken (or the transceivers are junk).

The midplane through connectors need to be modeled and verified they do not mess up the balance, impedance, etc. but otherwise this arrangement should work error free at any rate supported by our devices (up to 10 Gbs). With no long paths, you have the best situation: no loss to speak of.

Aust> On a different topic, what kind of error rate can I expect at 2.24 GB/s? Two

Is there any simple way to verify that a design actually does get such a low error rate?

The fiber guys have a neat trick. They insert enough attenuation so they get enough errors to measure, then back calculate the expected error rate without the attenuation. Theory and practice agree well.

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?? Well in communication theory books they assume that if there is noise that there is a chance > 0 that there will be an error in a period of time >0, this is just a matter of physics and mathematics. Same physics say that noise of 0 is only possible at extreme conditions, so I would say even a well designed link has errors, every logic circuit will very very rarely generate levels even if noise margins are high.

Best Regards, Roel