Hi All, I am trying to sim my design that deals with data transfer between my FPGA and a microcontroller with a 16-bit multiplexed data/address bus. In my design, I am using flags (data_in_enable, data_out_enable) to pick/put data from/onto the bus. Does anyone have an idea how to model the simulation (especially Procssor read cycle) I appreciate all the responses Thanks Morpheus
I would say Bus Functional Model (BFM).
Try a google of BFM in tis group for a start.
-Newman
Thanks Newman, I couldnt find anything on BFMs, but, I figured out what the problem with my design was. I was not tri-stating the bus while mimicing the processor functionality in my sim
-Morpheus
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