I'm looking at using a V2P RocketIO transmitter to synthesize a clock by bypassing the 8B10B encoder and feeding it 01010101 data words. I would vary the output clock frequency by varying the reference clock and/or the data pattern (00110011, 00001111, etc.). Is there any reason this would not work?
Thanks,
Robert
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I see no reason to doubt this. In fact, I intend to do the same thing. Note that in V2Pro the parallel interface is 10 or 20 bits wide, not 8 or 16 bits. This requires some digital trickery once you go beyond 4-bit patterns on the parallel side. Let me know if you run into any snags... Peter Alfke
I was actually thinking about implemeting something similar, but for direct RF modulation. Plan was to have m-phases of a clock as the data pattern, update it at the modulation rate and bandpass filter the output. Haven't tried it out yet, but I imagine you end up with M-PSK around the carrier. Unfortunately Your maximum RF frequency drops precipitously as m-increases. Yeah, it's probably easier to use an LO and a mixer, but getting BPSK through S -band would be pretty nifty coming from an FPGA. Anyone tried this or any comments on feasibility?
--Josh
16patterns
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