Reducing Clock Speed

In the spirit of friendly competition let me tell you that Xilinx Virtex-II hs no problem with this. You just tell the DCM to multiply the

And the Stratix or Cyclone Nios Development Board that was mentioned should be able to implement a similar frequency ratio with the Altera PLLs. Since, after all, that's the silicon he's using.

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"Use the PLL on your Nois development board's Altera chip." Please see the altera documentation on the altpll megafunction

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A lot better. at least this answer was specific to my question ;o) Thanks

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(I'm assuming you're using the Nios Dev Board)

It's easy. Just type in 48 MHz as the speed in the SOPC builder for your Nios processor, then double click on the PLL that runs the Nios and goto clock C0 screen and enter 24 and 25 for the multiplier and divisor. (I did this to change my C0 to 68 MHz just to see if it would run that fast - no problem!)

You should also be able to use clock C1 as well and then not have to alter the Nios's C0 clock. You could also probably alter the already hooked up E0 clock, but I don't know the details.

You probably solved this all by now. If you use Nios in the title I will pick up on it quickly. I am working on a Nios project and would like to discuss as many aspects of this technology as possible.

I'd like to hear about your USB progress. We're using an external chip on our custom board, but would be interested in a IP Core implementation.

Ken

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Hi Ken Thanks for the response. I actually got the 48mhz to work but still bit confused on C1 and E0 clocks (in PLL) but no worries, i guess I'll try and figure that out soon.

Regarding USB Implementation, I'm still trying my level best to get it to work. Basically I'm trying to get this core working that was mentioned on this newsgroup sometime back (Japanese version). It does not require any hardware, but i'm not able to make any progress on it. I have added my own PLL and connection the outputs to the leds (for debugging), and there are 2 leds that go on/off (USBEN and USBENLED), but becasue of no commenting i have very slight idea as to what's going on.

Ken if you are interested in knowing what i have got with regards to USB comm u are welcome to send me a mail @ snipped-for-privacy@mailcity.com with USB/Nios as the subject. I'll be more than happy to send you my progress (though it's bit slow)

Regares

Hi SneakerNet (probably not the name your parents gave you ;-)),

In addition to the aforementioned PLL megacore user's guide, I'd also suggest you take a peak at Chapter 6 of the Cyclone data book. You can find it here:

This Chapter discusses the 1 or 2 PLLs present in Cyclone. They are identical to the Fast PLLs present in the Stratix family. Each PLL provides you with three clocks that are generated off of one reference clock. There are two internal clocks (C0 and C1) and one external clock (E) that is fed to pin for use on your board. The three outputs share a common clock pre-scale (N) and divider (M). Each output can be independently post-scaled (G0/G1/E counters), and can be phase shifted relative to a reference clock (usually a fed back clock from the core).

The relationship of the clock frequencies is as follows:

f(C0) = f(In) * M/N/G0 f(C1) = f(In) * M/N/G1 f(E) = f(In) * M/N/E

But this is detail. I believe all you need to do is use the PLL MegaWizard and tell it the frequencies you'd like the PLL to generate and it will pick the appropriate M, N, G0, G1, and E values for you.

Regards,

Paul Leventis Altera Corp.

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Hi Paul, Yeah haha on the name bit LOL Anyway yeah i got the pll to work though the megawizard . However thanks for the indepth explanation, as I like to understand whats going on (and was getting confused regarding C0, C1, and E0). I 'll take a peak at the link you have given me.

Thanks Paul.

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