I've gotten the following code for the baudrate generator from opencores
I've created a Test Bench Waveform for it from my ISE.
Using single clock, Rising edge, Clock High/Low time as 3, Input setup/ Output Valid delay/ Offset as 0
when i run it in modelsim, I dont get any errors, neither do I get any waves from baud_x_en or baud_en.
======================
-----------------------------------------------------------------------------
-- Filename: am_baud_rate_gen.vhd
--
-- Description:
-- a paramatizable baud rate generator
--
-- input a 'high speed' clock, and get out a clock enable of x times the baud rate, and the baud rate.
-- paramiters are the high speed clock frequency, the baud rate required, and the over sample needed.
--
-- works by having two counters,
-- fast counter, counts down to x time baud rate
-- slow counter, then divides this to give baud rate.
--
--
-- Copyright (c) 2007 by Andrew Mulcock
-- an OpenCores.org Project
-- free to use, but see documentation for conditions
--
-- Revision History:
-- Revision Date Author Comment
-- -------- ---------- --------- -----------
-- 1.0 26/Nov/07 A Mulcock Initial revision
--
----------------------------------------------------------------------------- library ieee ; use ieee.std_logic_1164.all ; use ieee.numeric_std.all ;
entity am_baud_rate_gen is generic( baudrate : integer := 115200; clock_freq_mhz : real := 200.0; over_sample : integer := 4 ); port( clk : in std_logic; rst : in std_logic; baud_x_en : out std_logic; baud_en : out std_logic ); end entity;
-- ==========================================================================================
architecture baud_rtl of am_baud_rate_gen is
-- calculate from the clock freq, the baud rate, and the over sample ratio
-- the size and count of the two counters.
constant div_ratio_real : real := ( clock_freq_mhz * 1000000.0) / ((real(baudrate) * real(over_sample)) ); constant div_ratio_int : integer := integer ( div_ratio_real - 0.5);
-- 0.5 gives rounding up / down constant over_sample_ratio : integer := over_sample -1; constant max_count : integer := div_ratio_int;
signal fast_counter : integer range 0 to div_ratio_int; signal slow_counter : integer range 0 to over_sample_ratio; signal slow_cnt_en : std_logic;
begin
------------------------------------------------------------
------------ baud rate counter -----------------------------
------------------------------------------------------------
-- in an fpga, don't need to reset a wrap around counter,
-- but somepeople still like to for simulation
-- so comparmise and reset syncronously, as suits the syncronous counter.
process(clk) begin if rising_edge(clk) then if ( (rst = '1') or (fast_counter = 0) ) then fast_counter