Msg for Rudolf Usselmann

Hi Rudolf

This is with regards to your usb 1.1 function core from opencores.org.

Your USB clock needs a 48MHz clock speed. I have a Nios Development Board with a 50MHz oscillator. I'm using a PLL to drop the speed to 48.076923MHz (ratio of 25/26). Is that OK or does it have to be ditto 48MHz cuz that's the best that I can get.

Regards

Reply to
SneakerNet
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I don't know from the top of my head, you need to check the USB spec. Look at the max error rate they allow.

Please post follow up messages to the usb forum at OpenCores.org.

Thanks, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores ->

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Reply to
Rudolf Usselmann

it will receive 100% ok also with 50MHz clock I once tested accidently, not sure if the hosts will accept 50MHz transmit

48.08 will defenetly work both ways, not matter if it is withing spec range or not

Antti Lukats

Reply to
Antti Lukats

Thanks Rudolf and Antti

Reply to
SneakerNet

Hi Antti!

At work we have also worked on USB devices which are connected to a PC. In this case the tolerance of ceramic resonator can be too much. I am not sure about the exact figures, if I am not wrong the spec is about

+/-100ppm or slightly more. In some application notes you can find also statements like "should not work with ceramic resonators but no problems in practice". So using a 50MHz clock does not sound too much promising for me.

Best regards,

Christoph

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Reply to
Christoph Brinkhaus

Board

48.076923MHz

that's

transmit

range

Sure, I just said that the opencores usb1_phy DPLL tolerates 50MHz on the receive side! as I by accident did figure out.

nothing more. for any serious projec the specs should be followed of course!

antti

Reply to
Antti Lukats

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