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Clock triggered FSM

Hello boys,

I have got a small problem with my finite state machine which I have written in VHDL recently. I tried to create "intelligent" counter triggered by clock with frequency 2 Hz.

This counter is built in one state of FSM and is started by pushing a button on DE2 board.

Firstly, whole system is in IDLE state and if I push this button, state is changed to COUNTING and counter begin to be incremented and his current value is shown on LED display. After it reach value of modulo, the state COUNTING is left back to IDLE and the counter is set up to zero.

My problem is that the counter doesn´t work correctly - the counting value was too great. So I tried to solve it with this construction: if (clk_tick´event and clk_tick = 1) then.... , there are some errors by synthesis:

Error (10822): HDL error at Citac_FSM.vhd(57): couldn't implement registers for assignments on this clock edge

Error (10821): HDL error at Citac_FSM.vhd(62): can't infer register for "AUTOMAT:flg" because its behavior does not match any supported register model

Please, does somebody have an idea to solve it? And what is it correct way to write clock triggered FSM with two (or more) clock sources?

----------------------------------------------------------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all;

-- Entita ENTITY Counter_FSM IS GENERIC ( REGSIZE : integer := 8; -- range of counter MODULO : natural := 50 -- modulo value ); PORT ( CLK : IN STD_LOGIC; -- puls 50 MHz CLK_tick : IN STD_LOGIC; -- puls 2 Hz RESET : IN STD_LOGIC; -- reset READY : OUT STD_LOGIC; -- counter is ready to start START_C : IN STD_LOGIC; -- start of counting DOUT : OUT STD_LOGIC_VECTOR(REGSIZE - 1 downto 0) -- output ); END Counter_FSM;

--------------------------------------------------------------------------

--
-- Architecture of FSM
Reply to
electrin
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Am Montag, 18. Mai 2015 11:29:37 UTC+2 schrieb electrin:

You should spend some time trying to figure out what discrete logic you wou ld need to build your described logic, than figure out which logic you inte nd to have and how to modify VHDL code to reach this.

y

Two clock sources in same architecture is something you should avoid unless you are experienced. Each clock source builds one clock domain, signals co rssing between different clock domains require proper handling (google for clock domain crossing if you need more information about this topic)

In your case, you should use the fast clock to oversample the slow clock an d detect rising edge with a few clockcyles delay (of fast clock).

if rising_edge(fastclock) then slow_sr

Reply to
Thomas Stanka

Hi!

In general, the latching of a flip flop can only be triggered by one edge ( rising/faling) on clock signal, so when using multiple clocks things get tr icky fast - you can't use one clock to load a value into a register and the n another edge or clock to load a different value into the same register.

You can sometimes use the flip-flop's async set and reset signals, but it i s a slippery slope....

I think the easiest solution to your problem is rather than looking for an edge in the signal from the button, sample the signal in using the clock si gnal that runs the counter. Like this:

clocked_proc: process(clk) begin if rising_edge(clk) then ... update the rest of your state ... btn_two_cycles_ago

Reply to
Mike Field

I'm old school so when I write HDL code, I am actually "Describing Hardware" I picture in my head (the HD of HDL). Your hardware seems to have a split personality with part of it in the clocked portion of a process and part in the non-clocked portion. I expect this is not really what you intended. In fact, I expect your error is simply having a non-clocked portion of the process.

I suggest you don't use your current clock edge detect code and return to using rising_edge(clk).

formatting link
(clk)

I also suggest you not use clk_tick as a clock, but rather use it as an enable to the main clock, clk. Then your entire circuit will be synchronous and no need to deal with clock domain crossings.

--

Rick
Reply to
rickman

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