Hello,
I have an entity in VHDL that one of its ports is a record type. I am trying to create a test bench wave form to test the code but when ISE creating a test bench; it doesn't create the wave form for records. What is the problem and how can I solve it?
Regards
I would write my own testbench. The alternative is to change the port types or talk to Xilinx.
-- Mike Treseler
Hi,
Please refrain from using anything other than std_logic or std_logic_vector in the top level. Xilinx recommends using only std_logic and std_logic_vector at the top level. Even arrays are not supported as yet. The main reason is that there is no way for the back annotation tools to write out HDL that matches your top structure. Since the waveform tool is written to work with the rest of the ISE tools, it does not support this either. The workaround if you absolutely must have it be records is to write one manually, although be aware the only simulation you can do easily would be the RTL simulation.
Thanks Duth
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