Post-Place & Route Simulation with ISE

Hi all,

I am trying to make a post-place & route simulation of a very simple design.

In the "top.vhd "file there is declared an entity that contains some generics and the architecture.

entity top is generic( gen1 : real := 3.0; gen2 : std_logic; gen3 : std_logic ); port( clk : in std_logic; rst : in std_logic; input : in std_logic; output : out std_logic ); end top;

When I ask ISE to simulate a PPR simulation with modelsim it generates a file called "top_timesim.vhd". Then generates a "tb_top.tdo" where there are some modelsim commands that compile the "top.vhd" and "tb_top.vhd" files.

Modelsim generates a "not default binding for component top" error. I have seen the top_timesim.vhd file and the generics of my top are deleted!

Why can be this? Is there any way to avoid this?

Thanks in advance,


Note: I have rewriten the generics in "top_timesim.vhd" file and now it works well.

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Unfortunately, there is no way for the software to retain the original generics you defined in the code (at least not yet) and thus when netgen (the Xilinx ISE netlister) creates the entity for your top module, it can not recreate those generics in the declaration. Fortunately though, there is an easy way around this without having to edit the file or the test bench. If you run netgen with the -a switch (In the ISE GUI it is the advanced simulation model property, Generate Architecture Only) the netlist produced will not contain an entity declaration and only contain the architecture. What this allows you to do is retain the original entity declaration with the defined generics from your RTL code and bind the structural timing architecture to that. If you have already run a functional simulation using that RTL code for that project, then all you would need to do is flip this switch and that should fix the problem for you. As long as all of your ports are defined as std_logic/std_logic_vector, you should not have any problems with this. This is also an easy way to get around any top-level ports declared as a buffer rather than an out although I still highly suggest not to declare any port as a buffer in VHDL.

Good luck,

-- Brian

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Brian Philofsky

"arkaitz" escribió en el mensaje news:

i dont think you should use "generics" in a "top" entity that you want to synthesize (correct me if im wrong). I've heard that some tools accept them and use the default value if specified. what i do is to "wrap" the generic component, and instantiate it into a "wrapper" that doesnt contain any generics and where all generics have been fixed to constants defined in some package. It also eases simulation before and after synthesis, as you only have to switch wrappers (or architectures) in the testbench.

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Thanks both for the reply.

That's good to receive other people experiences.

I'll try with both tricks.



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